1. Field of the Invention
The present invention relates to the manufacturing of microcomponents. It more specifically relates to the forming of through vias in microcomponents and to a specific application to the forming of a fuel cell.
2. Description of the Related Art
FIG. 1 shows an example of the forming of a fuel cell using microelectronic techniques. This cell is formed on a silicon wafer 1 coated with a first thin insulating layer 2 and with a second thicker insulating layer 3. An opening is formed in a portion of insulating layer 3. In this opening are successively deposited a support 4, a lower catalyst layer 5, an electrolyte 6, and a upper catalyst layer 7. An electrode 10 enables taking a contact on the lower surface of the cell, more specifically on the catalyst support in the shown example. An upper electrode 11 enables taking a contact on upper catalyst layer 7. Electrodes 10 and 11 are provided with openings, and channels 12 are formed in silicon wafer 1 opposite to the openings in the lower surface metallization.
To operate the fuel cell, hydrogen is injected along arrow H2 on the lower surface side and air (carrying oxygen) is injected on the upper surface side. A hydrogen flow and an air flow may be ensured to have a good contact between the hydrogen and lower catalyst 5 and between the air and upper catalyst 7. In known fashion, with such a structure, a positive voltage is obtained on the upper electrode (on the oxygen side) and a negative voltage is obtained on the lower electrode (on the hydrogen side).
FIG. 1 shows a single fuel cell. In practice, on a same wafer 1, a large number of cells that can be assembled in series/parallel according to the desired use will be formed. Electrolyte 7 for example is a polymeric acid such as solid Nafion and the catalyst layers are for example carbon- and platinum-based layers. This is an example only. Various types of fuel batteries that can be formed as illustrated in FIG. 1 are known in the art.
In such a fuel cell, the power that can be provided is especially proportional to the surface area taken up by the cell in the silicon wafer plane.